The present invention relates to integrated circuits and, more particularly, to a transaction control circuit for synchronizing transactions across asynchronous clock domains.
Integrated circuits such as application specific integrated circuits (ASICs) often include a functional device, such as a microprocessor, which interfaces with one or more other functional devices that operate within different clock domains. For example, the microprocessor may be required to read and write configuration registers in a local area network (LAN) controller, which may be located on the same integrated circuit or on a separate integrated circuit. If the microprocessor is synchronized with a first clock signal and the LAN controller is synchronized with a second clock signal, which is asynchronous to the first clock signal, the handshaking signals passing back and forth between the microprocessor and the LAN controller must be resynchronized in each clock domain.
To initiate a transaction, such as a write or read operation, the microprocessor sets and later clears a transaction initiate bit (e.g. a read bit) in a register on the integrated circuit. The output of the register is synchronized with the second clock signal in the second clock domain and then provided to the LAN controller. The LAN controller responds by asserting a "busy" signal, which indicates that the transaction has not yet completed. In the case of a read transaction, the LAN controller asserts the busy signal until the requested data is ready to be retrieved, at which time the LAN controller deasserts the busy signal. The busy signal is resynchronized with the first clock signal and then provided to the microprocessor. The microprocessor periodically polls the busy signal to determine when the data is available.
Resynchronizing the initiate and busy signals results in a delay across the clock domains. Therefore, it is possible for the microprocessor to set the initiate signal and then poll the busy signal before the busy signal is set within the first clock domain. As a result, the microprocessor may determine prematurely that the requested transaction is complete and then read the data before the data is valid.
Traditional methods of implementing the handshaking of the initiate and busy signals between two clock domains to avoid transaction errors can become complex and consume a significant number of logic gates or software instructions. An improved structure and method of implementing the initiate and busy signals are desired.